The present invention relates to a semiconductor device having a high breakdown voltage characteristic and fabricating method thereof. In particular, a Metal Insulator Semiconductor (MIS) transistor has a structure having a high breakdown voltage characteristic without reducing the packing density of a semiconductor integrated circuit (IC) device. The MIS transistor also has an increasing amplication factor.
Recently, an IC device, having a control circuit for controlling a high voltage driving device such as a display device, is very widely used. In this IC device, certain characteristics relating to breakdown voltage, power drive ability, operation speed and amplification factor are required to be highly responsive to large scale integration, complex functions and high speeds of the high voltage driving device.
FIG. 1 is a schematic sectional side view for illustrating the structure of an enhancement type MIS transistor 101 which represents a typical prior art semiconductor device having a high breakdown voltage characteristic.
In FIG. 1, the MIS transistor 101 basically comprises a p.sup.+ type source region 7, a p.sup.+ type drain region 8 and a gate electrode 5. The source region 7 and the drain region 8 are formed on the surface of an n.sup.- type well 1. The gate electrode 5 is formed above the surface of the well 1 on a gate oxide layer 4. When a gate voltage is applied to the gate electrode 5, a channel region CH is formed under the gate electrode 5. Reference numeral 3 is an n-type channel stopper. A field oxide layer 2 is provided for separating a transistor region of the MIS transistor 101 from other electrical elements which are not shown in FIG. 1. An impurity block oxide layer 9 is formed on the source region 7, the drain region 8 and the gate electrode 5, and then an insulating film 10 is formed on the impurity block oxide layer 9 and the field oxide layer 2. The insulating film 10 is for insulating a source wiring 11, a gate wiring 12 and a drain wiring 13 respectively. The wirings 11, 12 and 13 are connected with the source region 7, the gate electrode 5 and the drain region 8 respectively, by removing part of the impurity block oxide layer 9 and the insulating film 10 which corresponds to each respective wiring. A p.sup.- type offset region 6 is located between the channel region CH and the drain region 8. The offset region 6 has a lower impurity concentration than the impurity concentration of the drain region 8 in order to have a high resistance. Due to the offset region 6, the depletion layer which is produced around the drain region 8 can be expanded. This results in the breakdown voltage being raised up to a high level at the drain region 8.
However, the prior art MIS transistor 101 has the following problems:
(1) The area occupied by the MIS transistor 101 tends to become enlarged because the offset length L.sub.OF of the offset region 6, which is located between the channel region CH and the drain region 8, must be lengthened in order to obtain a high breakdown voltage at the drain region 8.
(2) The operation speed and the amplification factor (62 ) of the MIS transistor 101 decrease because the offset length L.sub.OF is lengthened with increasing resistance thereof. The amplification factor .beta. is defined by the following formula: EQU .beta.=W/L..mu..epsilon..sub.ox /t.sub.ox
where,
.beta. is an amplifaction factor, PA1 W is a channel width, PA1 L is a channel length, PA1 .mu. is the mobility of carrier flowing through the channel, PA1 .epsilon..sub.ox is a dielectric contant of the channel, and PA1 t.sub.ox is the thickness of the gate oxide layer.
In the above formula, when the offset length L.sub.OF is lengthen, the mobility .mu. decreases, which results in a decrease in the amplification factor .beta..
(3) The width of the offset region 6 must be widened for driving the MIS transistor 101 at a high power because the conductance of the offset region 6 would decrease if only the length L.sub.OF were lengthened. This results in enlarging the area occupied by the MIS transistor 101.
(4) The channel length of the channel region CH is determined by the length of the gate electrode, so that the minimum channel length is limited by the minimum length of the gate electrode. The minimum length of the gate electrode is limited by the technical limitation of photo lithography. Therefore, the channel length has a limitation as long as the gate electrode is formed using photo lithography. In other words, high operation speed and high amplification factor .beta. are limited by the minimum length of the gate electrode as long as the gate electrode is formed by photo lithography.
(5) Generally, there are two types of MIS transistors: an enhancement type and a depletion type. An enchancement type MIS transistor is used for the amplifier as discussed above. Thus, the MIS transistor 101 is an enchancement type transistor and moreover it has a long channel length as stated above, so that the resistance of the MIS transistor 101 is high when the transistor is ON. Therefore, it is hard to obtain a high power operation and a high amplification factor .beta. of the MIS transistor 101.